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LTC1150 15V Zero-Drift Operational Amplifier with Internal Capacitors DESCRIPTIO
The LTC(R)1150 is a high-voltage, high-performance zero-drift operational amplifier. The two sample-and-hold capacitors usually required externally by other chopper amplifiers are integrated on-chip. Further, LTC's proprietary high-voltage CMOS structures allow the LTC1150 to operate at up to 32V total supply voltage. The LTC1150 has an offset voltage of 0.5V, drift of 0.01V/C, 0.1Hz to 10Hz input noise voltage of 1.8VP-P and a typical voltage gain of 180dB. The slew rate of 3V/s and a gain bandwidth product of 2.5MHz are achieved with 0.8mA of supply current. Overload recovery times from positive and negative saturation conditions are 3ms and 20ms, respectively. For applications demanding low power consumption, Pin 1 can be used to program the supply current. Pin 5 is an optional AC-coupled clock input, useful for synchronization. The LTC1150 is available in standard 8-lead, plastic dualin-line package, as well as an 8-lead SO package. The LTC1150 can be a plug-in replacement for most standard bipolar op amps with significant improvement in DC performance.
, LTC and LT are registered trademarks of Linear Technology Corporation.
FEATURES

High Voltage Operation: 16V No External Components Required Maximum Offset Voltage: 10V Maximum Offset Voltage Drift: 0.05V/C Low Noise 1.8VP-P (0.1Hz to 10Hz) Minimum Voltage Gain: 135dB Minimum PSRR: 120dB Minimum CMRR: 110dB Low Supply Current: 0.8mA Single Supply Operation: 4.75V to 32V Input Common Mode Range Includes Ground 200A Supply Current with Pin 1 Grounded Typical Overload Recovery Time 20ms
APPLICATIO S

Strain Gauge Amplifiers Electronic Scales Medical Instrumentation Thermocouple Amplifiers High Resolution Data Acquisition
TYPICAL APPLICATIO
1k
Single Supply Instrumentation Amplifier
160
1M V+ 1M V+ 2 7 6 1k 2
VOLTAGE NOISE DENSITY (nVHz)
140 120 100 80 60 40 20 0 10 100 1k 10k FREQUENCY (Hz) 100k
LTC1150 *TA02
- +
LTC1150 -VIN 3 4
- +
7 6 VOUT
LTC1150 VIN 3 4
GAIN = 1000V/V OUTPUT OFFSET 5mV TOTAL SUPPLY CURRENT DECREASES TO 400A WHEN BOTH PIN 1s ARE GROUNDED
LTC1150 *TA01
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Noise Spectrum
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1
LTC1150
ABSOLUTE
AXI U
RATI GS
Total Supply Voltage (V + to V -) ............................... 32V Input Voltage (Note 2) .............. (V + 0.3V) to (V- -0.3V) Output Short Circuit Duration .......................... Indefinite Burn-In Voltage ....................................................... 32V
PACKAGE/ORDER I FOR ATIO
TOP VIEW ISUPPLY 1 -IN 2 +IN 3 V- 4 8 CLOCK OUT 7 V+ 6 OUT EXT CLOCK 5 IN
ORDER PART NUMBER LTC1150CN8
ISUPPLY 1 -IN 2 +IN 3 V
-
N8 PACKAGE 8-LEAD PDIP TJMAX = 110C, JA = 130C/W J8 PACKAGE 8-LEAD CERDIP
OBSOLETE PACKAGE
Consider the N8 or S8 Package as an Alternate Source
LTC1150MJ8 LTC1150CJ8
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
PARAMETER Input Offset Voltage Average Input Offset Drift Long Term Offset Voltage Drift Input Offset Current CONDITIONS (Note 3) (Note 3)
The denotes the specifications which apply over the full operating temperature range otherwise specifications are at TA = 25C. VS = 15V, Pin 1 = Open, unless otherwise noted.
MIN
Input Bias Current
Input Noise Voltage Input Noise Current Common Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain Maximum Output Voltage Swing
RS = 100, 0.1Hz to 10Hz, TC2 RS = 100, 0.1Hz to 1Hz, TC2 f = 10Hz (Note 4) VCM = V- to 12V

VS = 2.375V to 16V RL = 10k, VOUT = 10V RL = 10k RL = 10k RL = 100k
2
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U
W
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(Note 1)
Operating Temperature Range LTC1150M (OBSOLETE).....................-55C to 125C LTC1150C .......................................... - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
TOP VIEW 8 CLOCK OUT V+ OUT EXT CLOCK IN
ORDER PART NUMBER LTC1150CS8
7 6 5
- +
4
S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 110C, JA = 200C/W
S8 PART MARKING 1150
LTC1150M TYP MAX 0.5 0.01 50 20 10 0.05 60 1.5 50 2.5
MIN
LTC1150C TYP MAX 0.5 0.01 50 20 10 1.8 0.6 1.8 200 0.5 100 1.0 10 0.05
UNITS V V/C nV/mo pA nA pA nA VP-P fA/Hz dB dB dB V
10 1.8 0.6 1.8 110 120 135 13.5
130 145 180 14.5
110 120 135 13.5 10.5/ -13.5
130 145 180 14.5
10.5/ -13.5 14.95
14.95
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LTC1150
ELECTRICAL CHARACTERISTICS
PARAMETER Slew Rate Gain Bandwidth Product Supply Current No Load No Load, Pin 1 = V - No Load CONDITIONS RL = 10k, CL = 50pF
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 15V, Pin 1 = Open, unless otherwise noted.
MIN LTC1150M TYP MAX 3 2.5 0.8 0.2
MIN
LTC1150C TYP MAX 3 2.5
UNITS V/s MHz
1.5 2
0.8 0.2 550
1.5 2
mA
Internal Sampling Frequency
550
Hz
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, Pin 1 = Open, unless otherwise noted.
PARAMETER Input Offset Voltage Average Input Offset Drift Long Term Offset Voltage Drift Input Offset Current Input Bias Current Input Noise Voltage Input Noise Current Common Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain RS = 100, 0.1Hz to 10Hz, TC2 RS = 100, 0.1Hz to 1Hz, TC2 f = 10Hz (Note 4) VCM = 0V to 2.7V VS = 2.375V to 16V RL = 10k, VOUT = 0.3V to 4.5V

CONDITIONS (Note 3) (Note 3)
MIN
LTC1150M TYP MAX 0.5 50 10 5 2.0 0.7 1.3 60 30 10 0.01 0.05
MIN
LTC1150C TYP MAX 0.05 0.01 50 10 5 2.0 0.7 1.3 60 30 10 0.05
UNITS V V/C V/mo pA pA VP-P fA/Hz dB dB dB V V/s MHz
106 120 115
130 145 180 0.15 to 4.85 0.02 to 4.97 1.5 1.8 0.4 1 1.5
106 120 115
130 145 180 0.15 to 4.85 0.02 to 4.97 1.5 1.8 0.4 300 1 1.5
Maximum Output Voltage Swing RL = 10k RL = 100k Slew Rate Gain Bandwidth Product Supply Current Internal Sampling Frequency Note 1: Absolute Maximum Ratings are those values beyond which life of the device may be impaired. Note 2: Connecting any terminal to voltages greater than V + or less than V - may cause destructive latch-up. It is recommended that no sources operating from external supplies be applied prior to power-up of the LTC1150. No Load
RL = 10k, CL = 50pF
mA Hz
300
Note 3: These parameters are guaranteed by design. Thermocouple effects preclude measurement of these voltage levels in high-speed automatic test systems. VOS is measured to a limit determined by test equipment capability. Note 4: Current Noise is calculated from the formula: IN = (2q * Ib) where q = 1.6 * 10 -19 Coulomb.
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LTC1150
TEST CIRCUITS
Offset Voltage Test Circuit
1M V+ 7 6 OUTPUT RL
10 100k 0.1F
DC-10Hz Noise Test Circuit
475k
1k
2
- +
LTC1150 3 4 V
-
-
LTC1150
158k
316k
475k
-
LT1012 0.1F 0.1F
+
+
TO X-Y RECORDER
LTC1150 *TC01
FOR 1Hz NOISE BW, INCREASE ALL THE CAPACITORS BY A FACTOR OF 10
LTC1150 *TC02
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
1000 900
SUPPLY CURRENT (A)
TA = 25C
800 700 600 500 400 300 200 4 8 12 16 20 24 28 32 36 TOTAL SUPPLY VOLTAGE, V+ TO V - (V)
LTC1150 * TPC01
SUPPLY CURRENT (A)
GAIN (dB)
Output Short-Circuit Current vs Supply Voltage
SHORT-CIRCIUT OUTPUT CURRENT, IOUT (mA)
6 4 2 0 -3 -6 -9 -12 -15 4 VOUT = V + ISINK PIN 1 = V - VOUT = V - ISOURCE PIN 1 = OPEN
TA = 25C
SUPPLY CURRENT (A)
GAIN (dB)
PIN 1 = V -
PIN 1 = OPEN
0
8 12 16 20 24 28 32 36 TOTAL SUPPLY VOLTAGE, V+ TO V - (V)
LTC1150 * TPC04
4
UW
Supply Current vs Temperature
1400 1200 1000 800 600 400 200 -55 VS = 15V
Gain/Phase vs Frequency
120 100 80 60 40 20 0 -20 VS = 15V CL = 100pF PHASE GAIN 100 60 80
PHASE (DEGREES)
120 140 160 180 200 1k 10k 100k FREQUENCY (Hz) 1M 220 10M
95 5 35 65 -25 AMBIENT TEMPERATURE (C)
125
-40 100
LTC1150 * TPC02
LTC1150 * TPC03
Supply Current vs RSET
1200 1000 800 600 400 200 VS = 15V TA = 25C 120 100 80
Gain/Phase vs Frequency
VS = 15V CL = 100pF PIN 1 = -15V PHASE 60 GAIN 40 20 0 -20 140 160 180 200 1k 10k 100k FREQUENCY (Hz) 1M 220 10M 120 60 80 100
PHASE (DEGREES)
1k
10k 100k RSET, PIN 1 TO V - ()
1M
-40 100
LTC1150 * TPC05
LTC1150 * TPC06
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LTC1150 TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias Current vs Supply Voltage
12 10
TA = 25C VCM = OV
INPUT BIAS CURRENT (pA)
OUTPUT VOLTAGE (Vp-p)
8 6 4 2 0 0 2
GAIN (dB)
4 6 8 10 12 14 16 SUPPLY VOLTAGE (V)
LTC1150 * TPC07
Input Bias Current vs Input Common Mode Voltage
40 30
INPUT BIAS CURRENT (pA)
VS = 15V TA = 25C -IB
20 10 0 -10 +IB -20 -30 -40 -15 5 10 -10 -5 0 INPUT COMMON MODE VOLTAGE (V)
LTC1150 * TPC10
INPUT BIAS CURRENT (pA)
-100
COMMON MODE RANGE (V)
CMRR vs Frequency
160 140 120
CMRR (dB)
80 60 40 20 0 1 10 100 1k FREQUENCY (Hz) 10k 100k
PSRR (dB)
100
100 80 60 40 20 0 1 10 NEGATIVE SUPPLY, PIN 1 = OPEN
POSITIVE SUPPLY, PIN 1 = V -
OFFSET VOLTAGE (V)
LTC1150 * TPC13
UW
15
Undistorted Output Swing vs Frequency
30 25 20 15 10 5 0 100
120 100
Gain/Phase vs Frequency
VS = 2.5V CL = 100pF PHASE GAIN 60 80 100
PIN 1 = V - RL = 10k
80 60 40 20 0 -20
PHASE (DEGREES)
120 140 160 180 200 1k 10k 100k FREQUENCY (Hz) 1M 220 10M
PIN 1 = FLOATING RL = 100k
1k
10k 100k FREQUENCY (Hz)
1M
-40 100
LTC1150 * TPC08
LTC1150 * TPC09
Input Bias Current vs Temperature
-1000 VCM = 0 VS = 15V
Common Mode Input Range vs Supply Voltage
15 TA = 25C 10 5 0 -5 -10
-IB -10
+IB
-1 -50 -25
0
25
50
75
100
125
-15
0
2.5
TEMPERATURE (C)
LTC1150 * TPC11
5 7.5 10 12.5 SUPPLY VOLTAGE (V)
15
LTC1150 * TPC12
PSRR vs Frequency
160 POSITIVE SUPPLY, PIN 1 = OPEN 140 120
Offset Voltage vs Sampling Frequency
10 VA = 15V TA = 25C PIN 1 = V -
8
6
4
PIN 1 = OPEN
NEGATIVE SUPPLY, PIN 1 = V -
2
0
100 1k FREQUENCY (Hz) 10k 100k
0
2k 1k SAMPLING FREQUENCY, fS (Hz)
3k
LTC1150 * TPC14
LTC1150 * TPC15
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5
LTC1150 TYPICAL PERFOR A CE CHARACTERISTICS
Offset Voltage Drift vs Sampling Frequency
100 90
OFFSET VOLTAGE DRIFT (nV/C)
VS = 15V
70 60 50 40 30 20 10 0 100 1k SAMPLING FREQUENCY, fS (Hz) 10k PIN 1 = OPEN
3
SAMPLING FREQUENCY (Hz)
80
10Hz PEAK-TO-PEAK NOISE (V)
Large-Signal Transient Response
VS = 15V, AV = 1, CL = 100pF, RL = 10k
Small-Signal Transient Response, Pin 1 = V -
VS = 15V, AV = 1, CL = 100pF, RL = 10k, PIN 1 = V -
6
UW
LTC1150 * TPC16
10Hz p-p Noise vs Sampling Frequency
4
Sampling Frequency vs Temperature
900 VS = 15V
VS = 15V TA = 25C
800 700 600 500 400
2
1
0 100
1k SAMPLING FREQUENCY, fS (Hz)
10k
300 -55
95 5 35 65 -25 AMBIENT TEMPERATURE (C)
125
LTC1150 * TPC17
LTC1150 * TPC18
Large-Signal Transient Response, Pin 1 = V -
Small-Signal Transient Response
VS = 15V, AV = 1, CL = 100pF, PIN 1 = V -
VS = 15V, AV = 1, CL = 100pF, RL = 10k
Overload Recovery from Negative Saturation
Overload Recovery from Positive Saturation
VS = 15V, AV = -100, 2ms/DIV
VS = 15V, AV = -100, 2ms/DIV
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LTC1150 TYPICAL PERFOR A CE CHARACTERISTICS
0.1Hz to 10Hz Noise, V = 15V, TA = 25C, Internal Clock
1V
1s
0.1Hz to 10Hz Noise, V = 15V, TA = 25C, fS = 1800Hz
1V
1s
0.1Hz to 1Hz Noise, V = 15V, TA = 25C, Internal Clock
500nV
10s
UW
2.0VP-P
10s
LTC1150 * TPC25
1.0VP-P
10s
LTC1150 * TPC26
700nVP-P
100s
LTC1150 * TPC27
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LTC1150 TYPICAL PERFOR A CE CHARACTERISTICS
0.1Hz to 1Hz Noise, V = 15V, TA = 25C, fS = 1800Hz
500nV
10s
PI DESCRIPTIO S
ISUPPLY (Pin 1): Supply Current Programming. The supply current can be programmed through Pin 1. When Pin 1 is left open or tied to V+, the supply current defaults to 800A. Tying a resistor between Pin 1 and Pin 4, the negative supply pin, will reduce the supply current. The supply current, as a function of the resistor value, is shown in Typical Performance Characteristics. -IN (Pin 2): Inverting Input. +IN (Pin 3): Noninverting Input. V- (Pin 4): Negative Supply. EXT CLOCK IN (Pin 5): Optional External Clock Input. The LTC1150 has an internal oscillator to control the circuit operation of the amplifier if Pin 5 is left open or biased at any DC voltage in the supply voltage range. When an external clock is desirable, it can be applied to Pin 5. The applied clock is AC-coupled to the internal circuitry to
8
UW
300nVP-P
100s
LTC1150 * TPC28
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8-Pin Packages
simplified interface requirements. The amplitude of the clock input signal needs to be greater than 2V and the voltage level has to be within the supply voltage range. Duty cycle is not critical. The internal chopping frequency is the external clock frequency divided by four. When frequency of the external clock falls below 100Hz (internal chopping at 25Hz), the internal oscillator takes over and the circuit chops at 550Hz. OUT (Pin 6): Output. V+ (Pin 7): Positive Supply. CLOCK OUT (Pin 8): Clock Output. The signal coming out of this pin is at the internal oscillator frequency of about 2.2kHz (four times the chopping frequency) and has voltage levels at VH = VS and VL = VS - 4.6. If the circuit is driven by an external clock, Pin 8 is pulled up to VS.
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LTC1150
APPLICATIO S I FOR ATIO
ACHIEVING PICOAMPERE/MICROVOLT PERFORMANCE Picoamperes
In order to realize the picoampere level of accuracy of the LTC1150, proper care must be exercised. Leakage currents in circuitry external to the amplifier can significantly degrade performance. High quality insulation should be used (e.g., Teflon, Kel-F); cleaning of all insulating surfaces to remove fluxes and other residues will probably be necessary-particularly for high temperature performance. Surface coating may be necessary to provide a moisture barrier in high humidity environments. Board leakage can be minimized by encircling the input connections with a guard ring operated at a potential close to that of the inputs: in inverting configurations the guard ring should be tied to ground; in noninverting connections to the inverting input. Guarding both sides of the printed circuit board is required. Bulk leakage reduction depends on the guard ring width. Microvolts Thermocouple effects must be considered if the LTC1150's ultralow drift is to be fully utilized. Any connection of dissimilar metals forms a thermoelectric junction producing an electric potential which varies with temperature (Seebeck effect). As temperature sensors, thermocouples exploit this phenomenon to produce useful information. In low drift amplifier circuits the effect is a primary source of error. Connectors, switches, relay contacts, sockets, resistors, solder, and even copper wire are all candidates for thermal EMF generation. Junctions of copper wire from different manufacturers can generate thermal EMFs of 200nV/C--four times the maximum drift specification of the LTC1150. The copper/kovar junction, formed when wire or printed circuit traces contact a package lead, has a thermal EMF of approximately 35V/C--700 times the maximum drift specification of the LTC1150. Minimizing thermal EMF-induced errors is possible if judicious attention is given to circuit board layout and component selection. It is good practice to minimize the
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number of junctions in the amplifier's input signal path. Avoid connectors, sockets, switches, and relays where possible. In instances where this is not possible, attempt to balance the number and type of junctions so that differential cancellation occurs. Doing this may involve deliberately introducing junctions to offset unavoidable junctions. Figure 1 is an example of the introduction of an unnecessary resistor to promote differential thermal balance. Maintaining compensating junctions in close physical proximity will keep them at the same temperature and reduce thermal EMF errors.
NOMINALLY UNNECESSARY RESISTOR USED TO THERMALLY BALANCE OTHER INPUT RESISTOR LEAD WIRE/SOLDER COPPER TRACE JUNCTION
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+
LTC1150 RESISTOR LEAD, SOLDER, COPPER TRACE JUNCTION OUTPUT
-
LTC1150 *AI01
Figure 1. Extra Resistors Cancel Thermal EMF
When connectors, switches, relays and/or sockets are necessary, they should be selected for low thermal EMF activity. The same techniques of thermally-balancing and coupling the matching junctions are effective in reducing the thermal EMF errors of these components. Resistors are another source of thermal EMF errors. Table 1 shows the thermal EMF generated for different resistors. The temperature gradient across the resistor is important, not the ambient temperature. There are two junctions formed at each end of the resistor and if these junctions are at the same temperature, their thermal EMFs will cancel each other. The thermal EMF numbers are approximate and vary with resistor value. High values give higher thermal EMF.
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LTC1150
APPLICATIO S I FOR ATIO
Table 1. Resistor Thermal EMF
RESISTOR TYPE Tin Oxide Carbon Composition Metal Film WireWound Evenohm Manganin
THERMAL EMF/C GRADIENT ~mV/C ~450V/C ~20V/C ~2V/C ~2V/C
PACKAGE-INDUCED OFFSET VOLTAGE Package-induced thermal EMF effects are another important source of errors. It arises at the copper/kovar junctions formed when wire or printed circuit traces contact a package lead. Like all the previously mentioned thermal EMF effects, it is outside the LTC1150's offset nulling loop and cannot be cancelled. Metal can H packages exhibit the worst warm-up drift. The input offset voltage specification of the LTC1150 is actually set by the package-induced warm-up drift rather than by the circuit itself. The thermal time constant ranges from 0.5 to 3 minutes, depending on package type. ALIASING Like all sampled data systems, the LTC1150 exhibits aliasing behavior at input frequencies near the sampling frequency. The LTC1150 includes a high-frequency correction loop which minimizes this effect; as a result, aliasing is not a problem for most applications. For a complete discussion of the correction circuitry and aliasing behavior, please refer to the LTC1051/53 data sheet. SYNCHRONIZATION OF MULTIPLE LTC115O'S When synchronization of several LTC1150's is required, one of the LTC1150's can be used to provide the "master" clock to control over 100 "slave" LTC1150's. The master clock, coming from Pin 8 of the master LTC1150, can directly drive Pin 5 of the slaves. Note that Pin 8 of the slave LTC1150's will be pulled up to VS. If all the LTC1150's are to be synchronized with an external clock, then the external clock should drive Pin 5 of all the LTC1150's.
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LEVEL SHIFTING THE CLOCK Level shifting is needed if the clock output of the LTC1150 in 15V operation must interface to regular 5V logic circuits. Figures 2 and 3 show some typical level shifting circuits. When operated from single 5V or 5V supplies, the LTC1150 clock output at Pin 8 can interface to TTL or CMOS inputs directly. LOW SUPPLY OPERATION The minimum supply for proper operation of the LTC1150 is typically below 4.0V (2.0V). In single supply applications, PSRR is guaranteed down to 4.7V (2.35V) to ensure proper operation down to the minimum TTL specified voltage of 4.75V.
15V 10k 2 7 8 6 LOGIC CIRCUIT 10k 5V
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- +
LTC1150 3 4 -15V
LTC1150 * AI02
Figure 2. Output Level Shift (Option 1)
15V 100pF
5V 10k
5V
2
- +
7 8 6 LOGIC CIRCUIT
LTC1150 3 4 -15V
10k
GND
LTC1150 * AI03
Figure 3. Output Level Shift (Option 2)
LTC1150
TYPICAL APPLICATIO S
SINGLE POINT SENSE GROUND
APPLICATION: TO FORCE TWO GROUND POINTS IN A SYSTEM WITHIN 5V
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Low Level Photodetector
15pF
1M HP 5082-4204 2 IP V+
10
- +
7 6
10k OUTPUT = IP * 10 9
LTC1150 3 4
LTC1150 * TA03
Ground Force Reference
1k 15V 2 15V 1000pF 6
- +
7
LTC1150 3 4 -15V
LT1010
-15V
FORCED GROUND
LTC1150 * TA04
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LTC1150
TYPICAL APPLICATIO S
Paralleling to Improve Noise
CLK IN 10k 10 MEASURED NOISE VOS = 1.1V CLK 10k FREE RUN CLK DRIVEN 1800Hz 10Hz = 700nVP-P 1Hz = 200nVP-P VOS = 10V 10Hz = 360nVP-P 1Hz = 160nVP-P
10
10
IN
10
LTC1150 * TA05
R2
2
-
LTC1150 6 -IR1 R2C 30pA R2 I R1
3
+
VOUT = 5V IR1
I LOAD R1
ERROR
12
+
U
-
LTC1150
+
10k
-
LTC1150
10k
25k
+
10k
- -
LTC1150 10k LTC1150 VOUT = 10k VIN
+
+
10k
-
LTC1150
10k
+
Battery Discharge Monitor
OPEN AT t = 0
C
t
+
LTC1150 * TA06
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LTC1150
PACKAGE DESCRIPTIO
CORNER LEADS OPTION (4 PLCS)
.045 - .068 (1.143 - 1.650) FULL LEAD OPTION .300 BSC (7.62 BSC)
.008 - .018 (0.203 - 0.457)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS
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J8 Package 8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
.405 (10.287) MAX 8 7 6 5 .005 (0.127) MIN .023 - .045 (0.584 - 1.143) HALF LEAD OPTION .025 (0.635) RAD TYP 1 2 3 .220 - .310 (5.588 - 7.874) 4 .200 (5.080) MAX .015 - .060 (0.381 - 1.524) 0 - 15 .045 - .065 (1.143 - 1.651) .014 - .026 (0.360 - 0.660) .100 (2.54) BSC .125 3.175 MIN
J8 0801
OBSOLETE PACKAGE
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13
LTC1150
PACKAGE DESCRIPTIO
.300 - .325 (7.620 - 8.255)
.008 - .015 (0.203 - 0.381) +.035 .325 -.015
(
8.255
+0.889 -0.381
)
INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
NOTE: 1. DIMENSIONS ARE
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N8 Package 8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400* (10.160) MAX 8 7 6 5 .255 .015* (6.477 0.381) 1 2 3 4 .130 .005 (3.302 0.127) .045 - .065 (1.143 - 1.651) .065 (1.651) TYP .120 (3.048) .020 MIN (0.508) MIN .018 .003 (0.457 0.076)
N8 1002
.100 (2.54) BSC
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LTC1150
PACKAGE DESCRIPTIO U
S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 - .197 (4.801 - 5.004) NOTE 3 8 7 6 5
.045 .005 .050 BSC N
N
.245 MIN
.160 .005
.228 - .244 (5.791 - 6.197)
.150 - .157 (3.810 - 3.988) NOTE 3 N/2
1
2
3
N/2
.030 .005 TYP RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
.010 - .020 x 45 (0.254 - 0.508) .008 - .010 (0.203 - 0.254)
0- 8 TYP
.053 - .069 (1.346 - 1.752)
.004 - .010 (0.101 - 0.254)
.016 - .050 (0.406 - 1.270)
NOTE: 1. DIMENSIONS IN
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.014 - .019 (0.355 - 0.483) TYP
.050 (1.270) BSC
SO8 0502
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1150
TYPICAL APPLICATIO
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
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DC Stabilized, Low Noise Amplifier
15V 3 INPUT 2 7 LTC1150 6
+ -
4 -15V 0.01F
15V
130 3 1
68 7 8 LT1028 6 15V
+ -
100k
OUTPUT 10k (A = 1000)
2
4 -15V
10
LTC1150 * TA07
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www.linear.com
LINEAR TECHNOLOGY CORPORATION 1991

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Price & Availability of LTC115003

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